Show HN: Esp32sim – Run ESP32 Firmware In The Browser

TL;DR

Before you orderOffer from Amazon

Get wellness gear delivered free with Prime

• Fast, free delivery on millions of items
• Prime Video, Amazon Music and more included
• Member-only deals all year

Start your free Prime trial →Free trial for eligible customers · Cancel anytime

As an affiliate, we earn on qualifying purchases.Hide

The Esp32sim GitHub project offers a Rust-based emulator that runs firmware for four ESP32-family chips, including the ESP32, S3, C3 and C6, in a browser using WebAssembly. Its author says the emulator boots the chips’ real mask ROM and second-stage bootloader alongside unmodified application images; reported hardware comparisons and decoder results have limits that the project documents.

The open-source project Esp32sim lets users run firmware for four Espressif chips—the ESP32, ESP32-S3, ESP32-C3 and ESP32-C6—in a browser, using a Rust emulator compiled to WebAssembly. Its GitHub documentation says the emulator boots each chip’s real mask ROM and second-stage bootloader and runs unmodified application images, offering developers a way to test supported projects without installing the emulator or connecting to a cloud service.

The project describes its core as instruction-level emulation across two processor families: Xtensa for the ESP32 and ESP32-S3, and RISC-V for the ESP32-C3 and ESP32-C6. The emulator models enough of each system-on-chip to boot through the ROM and bootloader into FreeRTOS and an application. The repository says it does not require patched firmware or firmware stubs.

Users can try the browser version at the project’s GitHub Pages site. The repository says it runs locally in the browser, with no cloud service or account. The project is also available as Rust command-line tools, with chip-specific binaries for the C3 and C6. Its code is released under the MIT license.

Hardware support differs by chip and board. The S3 model includes peripherals such as GPIO, UART and timers, while supported board configurations add displays, buttons, audio, camera and LED features. The C3 browser version is described as console-only. The C6 model includes an ST7789 display configuration and an energy-detection stand-in for 802.15.4 radio behavior. These are emulator models, not physical peripherals operating in the browser.

Testing Firmware Without a Board

Esp32sim could make some firmware checks easier to share: a developer can point someone to a browser-based demonstration rather than ask them to install a toolchain or obtain matching hardware. That may help with early development, debugging and project demonstrations, particularly for applications that use peripherals represented by the emulator.

Its reach depends on how closely the modeled hardware matches the target and on which devices an application uses. Browser access does not mean every ESP32 feature or project is supported, nor does simulated execution replace testing on physical boards. The project’s documentation gives users a starting point, while its varying chip maturity and documented test scope matter when judging results.

Four Chips, Shared Peripheral Models

The repository presents one shared machine framework for the supported chips, with separate processor emulators and chip-specific system models. It says the C3 and C6 reuse several peripheral models first used for the S3, including UART, timers, GPIO, SPI flash control, DMA and cryptographic hardware. Each chip still has its own memory map and interrupt or cache-related components.

The project’s browser interface is part of a larger codebase that also includes command-line tools, board models, example firmware and tests. Examples listed in the repository include Linux on the S3 and Wi-Fi demonstrations. The source describes the S3 as mature and the C3 and C6 implementations as drafts, with separate documentation for those chips. The classic ESP32 also has support for its ECO3 ROM on two LX6 cores.

“Each boots the real mask ROM, the real 2nd-stage bootloader and an unmodified application image.”

— Esp32sim project documentation on GitHub

Coverage and Test Limits

The repository reports decoder checks and comparisons against physical hardware, but it also qualifies what those figures establish. Its full-listing decoder results and hardware comparison counts come from earlier manual runs; external full-listing tests are excluded from CI. Continuous integration instead runs checked-in sampled decoder corpora and emulator golden-output tests.

For hardware comparisons, the project reports a JTAG trace for the S3 after timing-loop resynchronization, and console-output matches of 205 out of 208 lines for the C3 and 203 out of 204 for the C6. The documentation says the trace comparison normalizes window exceptions and resynchronizes delay loops, so it is not uninterrupted cycle-by-cycle agreement. It also says the Xtensa disassembler test excludes PIE operand comparisons. The source does not establish how the emulator performs across the full range of commercial firmware or unsupported peripherals.

The repository does not provide a publication date in the supplied material, independent evaluations, or a complete compatibility list for third-party projects. Its Wi-Fi and radio features are represented in software, and the C6 radio description includes a stand-in rather than a full account of physical radio behavior. Users should check the chip-specific documentation and test important firmware on its intended hardware.

Try the Browser Demo

The project points users to its browser demo and provides example firmware and chip-specific documentation for further testing. The repository does not specify a release schedule or a next milestone. Its documented next steps for readers are practical: select a supported chip or board, load an example or application image, and compare behavior with the corresponding physical hardware where accuracy matters.

Future confidence in the tool will depend on the project’s ongoing development, broader tests and clearer reports of compatibility across real applications. For now, the browser version is an accessible way to explore the supported models, while the documentation’s draft labels and stated test boundaries remain relevant to interpreting results.

Key Questions

Which ESP32-family chips does Esp32sim support?

The repository lists the ESP32, ESP32-S3, ESP32-C3 and ESP32-C6. The S3 is described as mature, while the C3 and C6 implementations are labeled drafts.

Does the browser emulator need an account or cloud service?

The project says its browser demo runs without a cloud service or account. It uses WebAssembly to run the emulator in the browser.

Can it run any ESP32 firmware?

The project says it can boot unmodified application images, but that does not establish compatibility with every firmware project or peripheral. Supported behavior depends on the chip and the hardware features modeled.

How has the emulator been tested against real chips?

The repository reports selected decoder checks and hardware comparisons, including console-line comparisons for the C3 and C6. It says some full-listing results came from manual runs and are not part of CI; its JTAG comparison also uses timing-loop resynchronization and is not uninterrupted cycle-by-cycle agreement.

Does browser testing replace a physical ESP32 board?

No. The emulator can help explore and test supported behavior, but its models do not prove that firmware will behave identically on physical hardware. The project’s documentation recommends understanding the test scope and checking important results on the target board.

Source: hn